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VeriFlow Technologies, Inc. is a design verification
company. Built from an established team of
experienced engineers, VeriFlow provides design
service expertise specializing on SOC/ASIC/FPGA
design verification and lab bring-up.
Created from a seasoned, successful and well
established team that has worked together for many
years across multiple ASIC designs, we believe that as
a team we can offer companies more value than the
sum of the individuals. The VeriFlow team have
developed and used best of the class verification
methods encompassing pre-silicon simulation, pre-
silicon hardware accelerated simulation, hardware
emulation, hardware and software co-simulation, lab
bringup, diagnostic development and manufacturing
test.
Depending on the needs of the client, VeriFlow can
help ASIC and FPGA design teams to efficiently create
verification environments, testplans, testbenches,
simulation models, develop software for simulation,
FPGA or lab bringup. In addition, VeriFlow can develop
verification strategies, conduct tool selection, help in
resource planning and project management.
Roland L. Lee
Takes on the lead role on various client projects:
* Integrated multiple 3rd Party IPs into a SOC ASIC
for IPTV. Developed System Verilog based testbench.
* Designed a System Verilog Testbench for a
wireless MAC.
* Helped verify an Ethernet packet processing
FPGA using a System Verilog Testbench.
* Developed System Verilog Testbench
Infrastructure for a complex SOC involving DPI
interaction with C-models and sw cosimulation.
Verified dma subsystems, datapath crossbars,
embedded cpus, and memory controller.
* Verified DDR Memory Controller in a 10Gbit
Ethernet system using Testbuilder and Verilog.
* Verified Ethernet MAC and interface block in a
pre-N 802.11 SOC ASIC using Vera and Verilog.
Before co-founding VeriFlow Technologies in 2004,
Roland Lee was Director of ASIC and FPGA
development at CIENA Corporation, managing the
ASIC design, FPGA design and diagnostic
departments for multiple product lines. At CIENA, he
also lead the ASIC design verification and diagnostic
development teams for the CoreDirector SONET
switch product and designed diagnostic and
manufacturing test systems for OC48, OC192 and
OC768 ASICs. Prior to being acquired by CIENA in
1999, he was the lead verification engineer on the
SONET Framer and Switch Fabric ASICs developed at
Lightera Networks, Inc.
From 1997-1998, he managed the Fibre Channel ASIC
development at G2 Networks and specialized in
design verification.
Roland Lee was Director of ASIC development at Axil
Computers, Inc. from 1994-1996 in which he built and
lead a team to develop an UltraSPARC based 4-way
multiprocessor chipset. Working closely with Sun
Microsystems and using Quickturn emulation, his
team was able to boot Solaris and run application
level diagnostics in the Lab with the Axil designs.
He managed the verification team at Axil from 1992-
1994.
From 1987 to 1992 he was with Sun Microsystems
where he was part of the original team that
developed the SunDragon multiprocessor with
Xerox Parc. He did the early architectural studies for
the cache design and system performance
evaluation and worked on ASIC design verification,
system modeling and system architecture. At
VeriFlow Technologies, he worked on several ASIC
design verification projects involving
hardware/software co-development and simulation,
SOC, Ethernet 802.3 and pre-standard 802.11n
designs.
Roland earned a bachelor's degree in electrical
engineering and computer science from UC
Berkeley and his MS and PhD degrees in computer
science from the University of Illinois, Urbana-
Champaign; thesis on Multiprocessor Cache
Architectures and Compilers.
Chandresh Patel
Before co-founding VeriFlow Technologies in 2004,
Chandresh Patel was involved in
SOC/ASIC/FPGA/System design verification projects
across many Bay Area companies spanning from
startups to midsize to fortune 500 company projects.
Chandresh Patel was also co-founder of CAESIUM,
Inc. which specialized in ASIC design verification
services from 1993 to 2000. Chandresh Patel has
over 25 years of experience in the design field
spanning boards, systems, microprocessor to ASIC
to SOC based products involving design IP and on-
chip buses, software/hardware co-simulation,
pre/post silicon simulation, acceleration and
emulation where appropriate based on the design
constraints.
Chandresh was involved in the team designing
microprocessor, micro-computer design, mini-
computer design and also Unix Mainframe design.
He has worked at hands on technical level as well as
in resource planning and project management level
for ASIC/system design verification projects.
Chandresh continues to provide project lead design
verification expertise as well as team building for a
large complex project.
Chandresh earned a MSCS in Computer Science
from Fairleigh Dickinson University in New Jersey in
1988 and a bachelor’s degree in electrical
engineering from SAICE, Pondicherry, India in 1979.
Shivi Sidhu
Shivi has two decades of experience setting up
design validation environments for various startups,
focusing on developing and integrating models and
tools to provide a seamless environment. Recent
projects include developing a seamless SONET test
verification/bring-up environment at Crimson
Microsystems using the Telecom Work Bench and
AiVi. He also setup the host testing for the Airgo
wireless MAC ASIC development and verified the
security processor, including developing TKIP test
vectors for the IEEE specifications. Shivi also also
recently verified the demand scheduler at Extreme
Packet Networks, Ottawa, by writing a detailed cycle-
accurate model of the device.
Shivi has a BSEE from the University of California,
Irvine.
Nehal Patel
At Matisse Networks Nehal has helped in the various
areas of Packet-Over-Fiber FPGA based system
design verification. At VeriFlow Technologies, Nehal
developed a PCI Express traffic generator and
checker providing transaction layer, data link layer
and phy layer level functions to verify PCI Express
designs. He worked on Verilog and C++ based
testbenches, test suites to verify PCI Express
designs and traffic generators/checkers and PCI
Express compliance test suites. At Ametek, Inc in
2001 to 2002, Nehal ported 68333 micro-controller
codes to the MPC555 micro-controller. He
successfully modified FFT code to achieve a 66%
timing drop-off.
In 2001, Nehal interned at CIENA Corporation where
he coded C++ and Perl scripts for ASIC verification,
participated in the documentation of test plans, and
developed utilities to provide regression status
reports.
Nehal earned a BS degree in Computer Engineering
from Lehigh University, Bethlehem, PA.
Marimuthu Thangaraj
Marimuthu is accomplished both in design and
verification of ASICs and FPGAs. He has more than 8
years of experience in analysis, design, verification
and bringup of ASIC/FPGA in networking and
telecom systems. He has experience in the following
protocols: IP QOS Diffserv class of services
Ethernet, ATM, HDLC, Ethernet Over SONET, and
SONET/SDH, PDH (E1); And in the following Chip-Chip
IO Protocols: Xilinx Rocket IO,SPI3, UTOPIA,UTOPIA+,
GMII, MII, TBI ,PCI ,PCI-X. Marimuthu has worked at
Anchiva Systems, Anagran Inc, CIENA Inc, and
Corona Networks.
Marimuthu holds a Bachelor of Engineering in
Computer Science and Engineering from PSG
College of Technology, Bharathiyar University, India,
1995.
Amit Mahajan
Amit has over 6 years of solid experience in design
verification and post-silicon bring-up of ASICs and
FPGAs for networking and telecom equipment. He
has extensive experience in design and
development of self-checking testbenches, test
plans, reference and bus functional models and
checkers. Amit was involved in module level and
system level verification of a high performance
network security ASIC. He was solely responsible for
the verification of a complex multi-processor cached
memory module. He also developed bus functional
and reference models in SystemC for system level
testbenches. Prior to that, Amit had a very
successfully 5 year tenure as lead verification
engineer at CIENA where he was involved in the
verification and bringup cycle of 7 ASICs and 2
FPGAs used in CIENA’s industry-first optical core
intelligent SONET switch. He designed test plans,
test benches, developed extensive testbenches in
Verilog, SystemC and C++ using both directed and
random self-checking testcases. He developed a
novel perl script to automatically generate a
configurable system level testbench with various
ASIC, FPGA and Boards.
Amit earned a BSEE from the University of Bombay,
India in 1995 and a MSEE from the University of
Nevada, Las Vegas in 1999.
company. Built from an established team of
experienced engineers, VeriFlow provides design
service expertise specializing on SOC/ASIC/FPGA
design verification and lab bring-up.
Created from a seasoned, successful and well
established team that has worked together for many
years across multiple ASIC designs, we believe that as
a team we can offer companies more value than the
sum of the individuals. The VeriFlow team have
developed and used best of the class verification
methods encompassing pre-silicon simulation, pre-
silicon hardware accelerated simulation, hardware
emulation, hardware and software co-simulation, lab
bringup, diagnostic development and manufacturing
test.
Depending on the needs of the client, VeriFlow can
help ASIC and FPGA design teams to efficiently create
verification environments, testplans, testbenches,
simulation models, develop software for simulation,
FPGA or lab bringup. In addition, VeriFlow can develop
verification strategies, conduct tool selection, help in
resource planning and project management.
Roland L. Lee
Takes on the lead role on various client projects:
* Integrated multiple 3rd Party IPs into a SOC ASIC
for IPTV. Developed System Verilog based testbench.
* Designed a System Verilog Testbench for a
wireless MAC.
* Helped verify an Ethernet packet processing
FPGA using a System Verilog Testbench.
* Developed System Verilog Testbench
Infrastructure for a complex SOC involving DPI
interaction with C-models and sw cosimulation.
Verified dma subsystems, datapath crossbars,
embedded cpus, and memory controller.
* Verified DDR Memory Controller in a 10Gbit
Ethernet system using Testbuilder and Verilog.
* Verified Ethernet MAC and interface block in a
pre-N 802.11 SOC ASIC using Vera and Verilog.
Before co-founding VeriFlow Technologies in 2004,
Roland Lee was Director of ASIC and FPGA
development at CIENA Corporation, managing the
ASIC design, FPGA design and diagnostic
departments for multiple product lines. At CIENA, he
also lead the ASIC design verification and diagnostic
development teams for the CoreDirector SONET
switch product and designed diagnostic and
manufacturing test systems for OC48, OC192 and
OC768 ASICs. Prior to being acquired by CIENA in
1999, he was the lead verification engineer on the
SONET Framer and Switch Fabric ASICs developed at
Lightera Networks, Inc.
From 1997-1998, he managed the Fibre Channel ASIC
development at G2 Networks and specialized in
design verification.
Roland Lee was Director of ASIC development at Axil
Computers, Inc. from 1994-1996 in which he built and
lead a team to develop an UltraSPARC based 4-way
multiprocessor chipset. Working closely with Sun
Microsystems and using Quickturn emulation, his
team was able to boot Solaris and run application
level diagnostics in the Lab with the Axil designs.
He managed the verification team at Axil from 1992-
1994.
From 1987 to 1992 he was with Sun Microsystems
where he was part of the original team that
developed the SunDragon multiprocessor with
Xerox Parc. He did the early architectural studies for
the cache design and system performance
evaluation and worked on ASIC design verification,
system modeling and system architecture. At
VeriFlow Technologies, he worked on several ASIC
design verification projects involving
hardware/software co-development and simulation,
SOC, Ethernet 802.3 and pre-standard 802.11n
designs.
Roland earned a bachelor's degree in electrical
engineering and computer science from UC
Berkeley and his MS and PhD degrees in computer
science from the University of Illinois, Urbana-
Champaign; thesis on Multiprocessor Cache
Architectures and Compilers.
Chandresh Patel
Before co-founding VeriFlow Technologies in 2004,
Chandresh Patel was involved in
SOC/ASIC/FPGA/System design verification projects
across many Bay Area companies spanning from
startups to midsize to fortune 500 company projects.
Chandresh Patel was also co-founder of CAESIUM,
Inc. which specialized in ASIC design verification
services from 1993 to 2000. Chandresh Patel has
over 25 years of experience in the design field
spanning boards, systems, microprocessor to ASIC
to SOC based products involving design IP and on-
chip buses, software/hardware co-simulation,
pre/post silicon simulation, acceleration and
emulation where appropriate based on the design
constraints.
Chandresh was involved in the team designing
microprocessor, micro-computer design, mini-
computer design and also Unix Mainframe design.
He has worked at hands on technical level as well as
in resource planning and project management level
for ASIC/system design verification projects.
Chandresh continues to provide project lead design
verification expertise as well as team building for a
large complex project.
Chandresh earned a MSCS in Computer Science
from Fairleigh Dickinson University in New Jersey in
1988 and a bachelor’s degree in electrical
engineering from SAICE, Pondicherry, India in 1979.
Shivi Sidhu
Shivi has two decades of experience setting up
design validation environments for various startups,
focusing on developing and integrating models and
tools to provide a seamless environment. Recent
projects include developing a seamless SONET test
verification/bring-up environment at Crimson
Microsystems using the Telecom Work Bench and
AiVi. He also setup the host testing for the Airgo
wireless MAC ASIC development and verified the
security processor, including developing TKIP test
vectors for the IEEE specifications. Shivi also also
recently verified the demand scheduler at Extreme
Packet Networks, Ottawa, by writing a detailed cycle-
accurate model of the device.
Shivi has a BSEE from the University of California,
Irvine.
Nehal Patel
At Matisse Networks Nehal has helped in the various
areas of Packet-Over-Fiber FPGA based system
design verification. At VeriFlow Technologies, Nehal
developed a PCI Express traffic generator and
checker providing transaction layer, data link layer
and phy layer level functions to verify PCI Express
designs. He worked on Verilog and C++ based
testbenches, test suites to verify PCI Express
designs and traffic generators/checkers and PCI
Express compliance test suites. At Ametek, Inc in
2001 to 2002, Nehal ported 68333 micro-controller
codes to the MPC555 micro-controller. He
successfully modified FFT code to achieve a 66%
timing drop-off.
In 2001, Nehal interned at CIENA Corporation where
he coded C++ and Perl scripts for ASIC verification,
participated in the documentation of test plans, and
developed utilities to provide regression status
reports.
Nehal earned a BS degree in Computer Engineering
from Lehigh University, Bethlehem, PA.
Marimuthu Thangaraj
Marimuthu is accomplished both in design and
verification of ASICs and FPGAs. He has more than 8
years of experience in analysis, design, verification
and bringup of ASIC/FPGA in networking and
telecom systems. He has experience in the following
protocols: IP QOS Diffserv class of services
Ethernet, ATM, HDLC, Ethernet Over SONET, and
SONET/SDH, PDH (E1); And in the following Chip-Chip
IO Protocols: Xilinx Rocket IO,SPI3, UTOPIA,UTOPIA+,
GMII, MII, TBI ,PCI ,PCI-X. Marimuthu has worked at
Anchiva Systems, Anagran Inc, CIENA Inc, and
Corona Networks.
Marimuthu holds a Bachelor of Engineering in
Computer Science and Engineering from PSG
College of Technology, Bharathiyar University, India,
1995.
Amit Mahajan
Amit has over 6 years of solid experience in design
verification and post-silicon bring-up of ASICs and
FPGAs for networking and telecom equipment. He
has extensive experience in design and
development of self-checking testbenches, test
plans, reference and bus functional models and
checkers. Amit was involved in module level and
system level verification of a high performance
network security ASIC. He was solely responsible for
the verification of a complex multi-processor cached
memory module. He also developed bus functional
and reference models in SystemC for system level
testbenches. Prior to that, Amit had a very
successfully 5 year tenure as lead verification
engineer at CIENA where he was involved in the
verification and bringup cycle of 7 ASICs and 2
FPGAs used in CIENA’s industry-first optical core
intelligent SONET switch. He designed test plans,
test benches, developed extensive testbenches in
Verilog, SystemC and C++ using both directed and
random self-checking testcases. He developed a
novel perl script to automatically generate a
configurable system level testbench with various
ASIC, FPGA and Boards.
Amit earned a BSEE from the University of Bombay,
India in 1995 and a MSEE from the University of
Nevada, Las Vegas in 1999.
VeriFlow Team USA
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Silicon Valley |